uboot: (firmwareOdroidC2/C4) don't invoke patch tool, use patches = [] instead

https://github.com/NixOS/nixpkgs/blob/master/pkgs/stdenv/generic/setup.sh#L948
this can do it nicely.

Signed-off-by: Anton Arapov <anton@deadbeef.mx>

pkgs/applications/science/electronics/vhd2vl/default.nix

@@ -0,0 +1,54 @@
+{ lib, stdenv
+, fetchFromGitHub
+, bison
+, flex
+, verilog
+, which
+}:
+
+stdenv.mkDerivation rec {
+  pname = "vhd2vl";
+  version = "unstable-2018-09-01";
+
+  src = fetchFromGitHub {
+    owner = "ldoolitt";
+    repo = pname;
+    rev = "37e3143395ce4e7d2f2e301e12a538caf52b983c";
+    sha256 = "17va2pil4938j8c93anhy45zzgnvq3k71a7glj02synfrsv6fs8n";
+  };
+
+  patches = lib.optionals (!stdenv.isAarch64) [
+    # fix build with verilog 11.0
+    ./test.patch
+  ];
+
+  nativeBuildInputs = [
+    bison
+    flex
+    which
+  ];
+
+  buildInputs = [
+    verilog
+  ];
+
+  # the "translate" target both (a) builds the software and (b) runs
+  # the tests (without validating the results)
+  buildTargets = [ "translate" ];
+
+  # the "diff" target examines the test results
+  checkTarget = "diff";
+
+  installPhase = ''
+    runHook preInstall
+    install -D -m755 src/vhd2vl $out/bin/vdh2vl
+    runHook postInstall
+  '';
+
+  meta = with lib; {
+    description = "VHDL to Verilog converter";
+    homepage = "https://github.com/ldoolitt/vhd2vl";
+    license = licenses.gpl2Plus;
+    maintainers = with maintainers; [ matthuszagh ];
+  };
+}

pkgs/applications/science/electronics/vhd2vl/test.patch

@@ -0,0 +1,35 @@
+--- a/translated_examples/fifo.v  1970-01-01 00:00:01.000000000 +0000
++++ a/temp/verilog/fifo.v 2022-05-11 03:44:43.173604945 +0000
+@@ -107,7 +107,7 @@
+   //--- Read address counter --------------
+   //---------------------------------------
+   assign add_RD_CE = (iempty == 1'b1) ? 1'b0 : (RD == 1'b0) ? 1'b0 : 1'b1;
+-  assign n_add_RD = (add_RD) + 4'h1;
++  assign n_add_RD = add_RD + 4'h1;
+   always @(posedge clk_RD, posedge rst) begin
+     if((rst == 1'b1)) begin
+       add_RD <= {5{1'b0}};
+diff -u '--exclude=Makefile' '--exclude-from=examples/exclude' translated_examples/test.v temp/verilog/test.v
+--- a/translated_examples/test.v  1970-01-01 00:00:01.000000000 +0000
++++ a/temp/verilog/test.v 2022-05-11 03:44:43.189604945 +0000
+@@ -125,7 +125,7 @@
+     endcase
+   end
+
+-  assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
++  assign code1[1:0] = a[6:5] ^ {a[4],b[6]};
+   // Asynch process
+   always @(we, addr, config1, bip) begin
+     if(we == 1'b1) begin
+diff -u '--exclude=Makefile' '--exclude-from=examples/exclude' translated_examples/withselect.v temp/verilog/withselect.v
+--- a/translated_examples/withselect.v    1970-01-01 00:00:01.000000000 +0000
++++ a/temp/verilog/withselect.v   2022-05-11 03:44:43.193604945 +0000
+@@ -33,7 +33,7 @@
+     endcase
+   end
+
+-  assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
++  assign code1[1:0] = a[6:5] ^ {a[4],b[6]};
+   assign foo = {(((1 + 1))-((0))+1){1'b0}};
+   assign egg = {78{1'b0}};
+   assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};